The present invention relates to performing metal deposition and global planarization of an integrated circuit substrate (IC) surface simultaneously. More particularly, the present invention relates to employing a modified chemical-mechanical polishing (CMP) apparatus to simultaneously perform metal deposition during global planarization of an integrated circuit (IC) substrate surface that is being processed according to the damascene process.
The damascene process, well known in the art and explained hereinafter, provides a metallization inlaid dielectric layer as opposed to having a metallization layer patterned above a dielectric layer. FIGS. 1A-1C show a portion of a surface of a partially fabricated IC substrate 10 that is processed to form a metal line and a via plug in a dielectric layer.
FIG. 1A shows the surface of a partially fabricated IC 10 including a dielectric layer 14, which is disposed above a first metallization layer 12 and includes a trench 16 and a via hole 18. As shown in FIG. 1A, trench 16 and via hole 18 are connected to each other in dielectric layer 14. Stated another way, trench 16 is a concave region that recesses inwardly into a top surface of dielectric layer 14 and is superimposed on via hole 18, which is an aperture through dielectric layer 14.
Partially fabricated IC 10 shown in FIG. 1A is typically formed by developing on the top surface of dielectric layer 14 a via mask, according to conventional photolithography, and then etching dielectric layer 14 from the top surface to a bottom surface to form via hole 18. Next, another mask, a trench mask, is similarly developed on dielectric layer 14 and dielectric layer 14 is etched to form trench 16. Those skilled in the art will recognize that trench 16 of FIG. 1A may be constructed by etching into the dielectric layer 14 before via hole 18 is formed using the same techniques described above or using a hard mask, e.g., a silicon nitride mask.
Next, a metallization layer 20 is blanket deposited on partially the fabricated IC substrate surface, as shown in FIG. 1B, filling trench 16 and via hole 18 of FIG. 1A to form a metal line 16' and a via plug 18', respectively. The IC substrate surface then undergoes chemical-mechanical polishing (CMP) to remove the excess metallization layer 20 deposited above dielectric layer 14 and above metal line 16'. CMP typically involves mounting an IC substrate, e.g., a semiconductor wafer, faced down on a substrate holder and rotating the substrate surface against a polishing pad mounted on a platen, which is in turn rotating or is in orbital state. A slurry containing a chemical that chemically interacts with the facing substrate layer and an abrasive that physically removes that layer is flowed between the substrate surface and the polishing pad or on the pad near the substrate surface.
After CMP concludes, partially fabricated IC 10 is typically substantially planar and ready for another deposition of a dielectric layer. Those skilled in the art will recognize that similar steps of dielectric and metal layer depositions, followed by etching or CMP may be carried out on the surface of partially fabricated IC 10 to completely fabricate an IC.
Unfortunately, the current damascene process described above suffers from several drawbacks. By way of example, the current process requires two separate steps for metal deposition and polishing, which steps are expensive to implement. Furthermore, the current process is also time-consuming and therefore lowers the throughput for the semiconductor fabrication process.
What is therefore needed is a process of rapidly and inexpensively forming metal lines and plugs on an IC substrate surface.